The invention relates generally to semiconductor device fabrication and, in particular, to methods of forming structures for use in atomic force probing, as well as structures for use in atomic force probing.
Atomic force probing is routinely used to locate and electrically characterize features in integrated circuits for performing root cause failure analysis of defective devices. In particular, failure analysis investigations can be conducted for sub-0.1 micron complementary metal-oxide-semiconductor (CMOS) technology to contact defective devices. Atomic force probing at the contact level of such CMOS devices permits accurate determination of basic transistor parameters such as transistor drive current in the saturation region (Idsat), threshold voltage in the linear region (Vtlin), and threshold voltage in the saturation region (Vtsat).
As the technology node shrinks, the physical defects that cause device failures also diminish in size. Because of their limited spatial resolution, it is difficult, if not impossible, to use other types of conventional probing to perform root cause failure analysis at advanced technology nodes. An atomic force probe tool is ideally suited to probe and electrically characterize transistors made with sub-0.1 micron CMOS technologies at the contact layer.
The atomic force probe tool consists of multiple atomic force heads configured to image in a contact mode using sharp probe tips composed of tungsten. The probe tips are scanned in unison across a small surface area of the integrated circuit, which has been delayered to expose the transistor contacts of interest. A force feedback loop is used to maintain a constant force pressing the probe tips against the surface. A nanometer resolution map of the topography of the surface structure is created from the scan. The transistor contacts of interest are identified in the topographic map and their locations are specified. The same probe tips are then used to probe these contacts and electrically characterize the transistor.
Sample preparation is required for probing an integrated circuit to remove overlying metallization levels of a back-end-of-line (BEOL) wiring structure so that an interlayer dielectric containing the contacts of interest for the defective device under investigation can be accessed. One approach for sample preparation is to partially delayer the BEOL wiring structure down to the interlayer dielectric by mechanical polishing to reveal the contacts of interest. Another sample preparation approach is to use a focused ion beam to drill small, deep contact holes through the various interlevel dielectrics to the lower metallization levels in order to access the transistor contacts.
Probe lifetime and image resolution are both limited by the ability of the force feedback loop to timely respond to interactions between the probe tip and the surface. Conventional sample preparation for atomic force probing provides a relatively rough surface topography that is not optimum for atomic force probing. Because the probing is performed in contact move, the probe tips are dragged along the surface. As a result, collisions with objects on the surface can damage the probe tip, which reduces the probe lifetime and the resolution.
After a sample is prepared for atomic force probing, the exposed metal can readily oxidize when exposed to atmosphere and sometimes in a day or less. The oxidation increases the probing resistance, which in turn increases significantly impacts the measurement results. Copper wires are readily prone to rapid oxidation.
Consequently, methods and structures for atomic force probing are needed that overcome these and other disadvantages of conventional atomic force probing techniques and structures.